The present invention relates generally to integrated circuit design, and more particularly, to generation of a mesh plane for a chip module design and a related file storage technique.
A mesh plane is a structure of interconnected lines in a cross-hatch pattern (90-degree relative angles) on a given layer of a single-chip or multiple chip module (SCM or MCM), used to tie power or ground vias together. A mesh plane provides both a means of lowering the inductance of the power/ground connections, and of providing noise shielding and power/ground coupling to the signal lines above and below the given layer. Mesh planes include difficult areas to design, such as a chipsite and other dense via regions, which require careful consideration to assure proper connections for the power and ground networks.
Conventionally, mesh planes are designed for an IC carrier design manually. In particular, mesh planes are conventionally designed by an additive approach in which features are added line-by-line to a field until the design is complete. This process is slow and tedious work. For example, FIG. 1 illustrates a particular sub-layout 10 of lines within a mesh plane. Each line within sub-layout 10 must be manually entered, which takes time and patience.
Another shortcoming of the above approach is that conventional IC carrier design tools store each line as a separate feature for storage purposes. Conventional chip module design tools also treat each “T” junction of active lines as a line break point 12. (Crossing of lines do not cause a similar segmentation). For example, sub-layout 10 includes twelve features in total: two crossed lines 14 at each corner and then four lines 16 coupling line break points 12 to a via 18 (size exaggerated so viewable) in the center. Each of these twelve lines or features are stored separately. An unfortunate result of this line-by-line storage approach is that as IC carrier design has increased in complexity, the ultimate IC design files have become very large, which makes storage difficult and may burden system resources, e.g., during revisions.
In view of the foregoing, there is a need in the art for a way to generate a mesh plane for an IC design that does not suffer from the problems of the related art.